The present disclosure relates to standard cell libraries used in design of semiconductor integrated circuits, and more particularly to formation of driving force sequences of libraries and cell layout configurations implementing the driving force sequences. Specifically, the present disclosure relates to standard cell libraries including geometric progression driving force sequences.
In design of a semiconductor integrated circuit, a standard cell library used as an ASIC design method includes some functions which are limited to basic logic functions such as an inverter, a buffer, a two-input NAND, a two-input NOR, a two-input AND, and a two-input OR. A transistor circuit performs a logic function in the form of a logic gate, which is registered as a standard cell. Cells with different driving force can be formed for each logic function by changing the sizes of transistors for driving output signals. In general, cells with a plurality of types of driving force are registered for a single logic function.
On the other hand, as a custom design method for designing a high-performance circuit, there exists the idea of limiting logic functions to basic ones to some extent, treating the functions as logic gates, and combining the logic gates to design the circuit. Such a method is suggested in, for example, Ivan Sutherland, Bob Sproull, and David Harris, Logical Effort: Designing Fast CMOS Circuits, Academic Press, 1999. Sutherland et al. use a custom design method, in which transistor sizes of gates are manually set to optimum sizes in a serial manner, each time when the transistors are provided in a circuit. Sutherland et al. describes as a basic design guideline that driving force of logic gates arranged in a continuous logical path is preferably geometrically increased from an input to an output of a path signal. This is widely known among custom designers as a guideline supported by a logical background and authors' accumulated experiences.
Conventionally, in a standard cell library, if reference driving force is [1], a driving force sequence of cells having the same logic function geometrically increases by two times like [½], [1], [2], [4], and [8]. Then, with an increasing demand for using an ASIC design method to a high-speed circuit design, higher driving force such as [16] and [32] is added, thereby extending a driving force sequence at the side of the higher driving force. Furthermore, with an increasing demand for low power consumption, it became known that the increasing rate of the driving force is preferably low to reduce cases using excessively great driving force, and thus intermediate driving force such as [3] and [6] is added. As a result, the driving force levels are [½], [1], [2], [3], [4], [6], [8], [16], and [32]. The increasing rates between the adjacent driving force levels are non-uniform, since rates 1.5 and 1.333 are included in addition to 2.0. Compared to the past, driving force sequences with greater variety of driving force are becoming common.
In recent years, the industry of designing a semiconductor large-scale integrated circuit has particularly strongly demanded for an improvement in a semi-custom design method, i.e., an ASIC design method using a standard cell library, so that the semi-custom design method is used in higher-performance circuit design which requires both of high speed and low power consumption in a high level. To achieve the objective, for example, David Chinnery and Kurt Keutzer, Closing the Gap Between ASIC & Custom, Kluwer Academic Publishers, 2002 provides some suggestions to actively introduce the idea of the custom design method into the ASIC design method.
Chinnery et al. focus on size design of a transistor as a possible improvement method which is left in design of a standard cell library. For example, Chinnery et al. suggest the process flow of: taking a usual ASIC design procedure using a standard cell library; and then, receiving delay analysis, selecting a cell of which speed needs to be increased to meet delay constraints, or a cell consuming excessive power at excessively high speed with respect to the delay constraints; and correcting an internal transistor size to use the selected cell in the design as a new cell. Chinnery et al. also report that this flow reduces circuit delay by 13.5% and power consumption by 18%. This example also shows the great importance and the advantage of strictly controlling the sizes of individual transistors in a cell in view of optimizing a standard cell library to design a high-performance circuit.
According to the suggested flow, since the size of the cell itself may change when correcting the sizes of the transistors within the cell, there is an inevitable problem of increasing excessive work of adding and redesigning new cells. To address this problem, for example, Japanese Patent Publication No. H09-107035 suggests a definition method of a library in which sizes of internal transistors can be freely redesigned under predetermined maximum size constraints, without changing the size of the cell or positions of input/output pins of the cell.